With the development of very-large-scale integration (VLSI), the critical dimension of ICs continues to decrease and the integration of ICs continues to increase, back end interconnections generally adopt wirings with three-dimensional architectures and multiple layers. Meanwhile, copper (Cu) interconnection has many advantages incomparable with aluminum interconnection for the fabrication of ICs at 130 nm technology node and below, and has thus become the dominant interconnection process. Damascene process is indispensable in the realization of multilayer copper interconnection structure. A Damascene process typically includes the steps of: depositing an insulating dielectric layer, etching conductive wire trenches and contact holes, depositing a diffusion barrier layer and a copper seed layer, copper electroplating, and chemical mechanical polishing (CMP) of copper.
Among these steps, the CMP step is the most critical part for the success of copper interconnections, because CMP is the only process which may achieve global planarization. However, in a Cu-CMP process, non-uniformity of copper wiring density will lead to defects, such as dishing 2 and erosion 1 shown in FIG. 1, in certain areas, for example, where wires are relatively wide, or where wiring densities are relatively high. These defects will affect post-CMP surface planarity and hence lower the production yield and reliability. On the other hand, in the case of multilayer wiring, CMP process itself also requires a good surface planarity, because surface non-planarity will accumulate with the increase of layers and may finally lead to the metal residue or defects, such as pooling and bridging, in certain areas during subsequent processes of forming copper interconnections.
In general practice, inserting dummy patterns into blank areas during wiring layout design is a practical way to improve surface planarity after a Cu-CMP process, the uniformity of wiring density throughout the whole metal layer surface can be improved. A high effectiveness of this method in Cu-CMP for processing interconnection layers has been confirmed in practical use.
However, in addition to the quality of the Cu-CMP process, the surface planarity of the copper interconnection layer is also related to the surface planarity of the contact hole layer located directly under the copper interconnection layer. Therefore, a method of improving the surface planarity of the contact hole layer is needed.